Advancements in the area of semiconductor integrated circuit fabrication have enabled the manufacturing of integrated circuits that have a high density of electronic components, wherein the electronic components include capacitors, diodes, resistors and transistors. As the density of electronic components on integrated circuits increases, the number and length of interconnect wirings between the electronic components also increase. However, a challenge arises wherein an increase in the number and length of interconnect wirings can cause an increase in circuit resistance-capacitance (RC) delay and power consumption, which can negatively impact circuit performance.
Three-dimensional (3D) integrated circuits have been created to address the challenge discussed above. Generally, in a typical fabrication process of 3D integrated circuits at least two wafers, each including an integrated circuit, are formed. The wafers are vertically stacked and bonded together, and the electronic components of the integrated circuits on the wafers are appropriately aligned. Vertically stacked wafers can reduce interconnect wiring length. In addition, deep through-silicon vias (TSVs) are formed to provide interconnections and electrical connectivity between the electronic components on the vertically stacked wafers. Thus, an increase in device density of integrated circuits and a reduction of total interconnection wiring length can be achieved using 3D integrated circuit technology.
However, fabricating and filling high aspect ratio TSVs without pinch-off has presented challenges. Pinch-off refers to build up of deposited material at an opening of a trench or a via hole (e.g., TSV). Pinch-off can result in void formation, wherein parts of a trench surface area and/or parts of a via hole (e.g., TSV) are not filled with the deposited material. Void formation can result in an open circuit if one or more voids formed are large enough to sever the interconnect structure. Thus, void formation can reduce integrated circuit performance, decrease reliability of interconnects, cause sudden data loss, and reduce the useful life of semiconductor integrated circuit products. In addition, pinch-off can result in entrapment of undesired process chemicals within a trench or a via hole (e.g., TSV).
Accordingly, despite achievements that have been made in 3D integrated circuit technology, to increase device density and reduce the length of interconnection wiring, the challenge of fabricating and filling high aspect ratio TSVs without void formation and chemical entrapment continues to persist.